1. Field
The present invention relates to technology for non-volatile storage.
2. Description of the Related Art
Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory typically utilize a charge storage region that is positioned above and insulated from a channel region in a semiconductor substrate. The charge storage region is positioned between source and drain regions. A control gate is provided over and insulated from the charge storage region. The threshold voltage of the transistor is controlled by the amount of charge that is retained in the charge storage region. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge in the charge storage region.
One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series, sandwiched between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a circuit diagram of one NAND string and FIG. 2 is a cross sectional view of the NAND string. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first (or drain) select gate 120 and a second (or source) select gate 122. Select gate 120 connects the NAND string to a bit line via bit line contact 126. Select gate 122 connects the NAND string to source line 128. Select gate 120 is controlled by applying the appropriate voltages to select line SGD. Select gate 122 is controlled by applying the appropriate voltages to select line SGS. Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate that form a floating gate stack. For example, transistor 100 has control gate 140 and floating gate 130. Transistor 102 includes control gate 142 and a floating gate 132. Transistor 104 includes control gate 144 and floating gate 134. Transistor 106 includes a control gate 146 and a floating gate 136. Control gate 140 is connected to word line WL3, control gate 142 is connected to word line WL2, control gate 144 is connected to word line WL1, and control gate 146 is connected to word line WL0. Each of the transistors (100, 102, 104, 106) of the NAND string are created on a common P-well. In some embodiments, the word lines are the control gates. Each of the transistors 100, 102, 104, 106 of the NAND have source and drain regions. For example, as depicted in FIG. 2, between each of the floating gate stacks are source/drain regions 160.
Note that although FIGS. 1 and 2 show four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, 64 memory cells, 128 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
Although FIGS. 1 and 2 show the transistors/memory cells of the NAND string having floating gates, in some embodiments other types of charge storage layers can be used. One example of a charge storage layer other than a floating gate is a charge trapping layer made from silicon nitride (“nitride”), or other suitable material.
When reading a flash memory device, such as a NAND flash memory device, a reference voltage is applied to the control gate and it is determined whether the transistor turns on. If the transistor turns on, then the threshold voltage is less than the reference voltage. The reference voltage typically corresponds to a demarcation between programmed and not programmed, or between different programmed states. More details about reading and programming flash memory can be found in U.S. Patent Application Publication 20070206426, incorporated herein by reference in its entirety.
Interference from neighboring devices or areas can cause an error when reading data stored in non-volatile storage. This interference will be explained with respect to FIG. 3,
FIG. 3 is a cross sectional view of three NAND strings, where the cross section is taken along the line AA of FIG. 2. Thus, FIG. 3 depicts a view along the word line direction (see arrow), with the bit line direction being in and out of the page. The first NAND string depicted in FIG. 3 includes channel 230, floating gate 202 and WL2. The second NAND string depicted in FIG. 3 includes channel 232, floating gate 132 and WL2. The third NAND string depicted in FIG. 3 includes channel 234, floating gate 204 and WL2.
Three sources of interference can negatively effect read operations. First, charge on floating gate 204 can effect the current in channel 232. Second, current flowing or charge existing in channel 234 can effect the current in channel 232. Third, if the lower portion 240 of Word Line WL2 is close enough to channel 232, then charge on WL2 can effect the current in channel 232. All three of these effects on the current in channel 232 can cause an error when reading data stored in floating gate 132.